The USENIX Association

2017 USENIX Vail Computer Elements Workshop

The USENIX Vail Computer Elements Workshop is a unique four day workshop that has been around for 47 years serving leading architects of the computer industry. This intentionally small workshop is intended to allow a lively interaction between the participants and the speakers. The agenda is 100% invited technical talks and the audience is mostly previous speakers. Past keynotes have been Seymour Cray, Gordon Moore, Burton Smith, and Ivan Sutherland.

The workshop will be held June 18 - 21, 2017 at the Christiania at Vail.

Andrew Herbert


This year's Keynote will be Rebuilding the Cambridge EDSAC by Andrew Herbert


Herbert received his Ph.D. in Computer Science from Cambridge University in 1978 for his work on “A Microprogrammed Operating System Kernel” and worked with Maurice Wilkes and Roger Needham and others on the “Cambridge Model Distributed System”. Later he joined Microsoft Research Cambridge as managing director and chairman of Microsoft Research EMEA. Herbert was appointed Officer of the Order of the British Empire (OBE) in the 2010 New Year Honours, and is a Fellow of the Royal Academy of Engineering. Now in retirement, Herbert is the director of a project to construct a working replica of the Cambridge EDSAC computer.

Registration is open here.

Preliminary Program

Next generation Atom core  -  Intel
Nervana - Deep Learning processor  -  Intel
Nano-Engineered Computing Systems Technology, or N3XT  -  Stanford
IBM Power9  -  IBM
OpenCAPI  -  IBM
Ryzen - AMD's new core  -  AMD
Intel's 3DNAND and 3DXP storage class products  -  Intel
Persistent Memory: The Benefits and the Challenges  -  Intel
The Next Step in Computing: Neuromemristive Processors  -  Knowm Inc
Evolutionary advances in memory, Revolutionary implications for applications  -  Sandisk
Motor Control for next generation HEV/EV  -  Renesas
4k/8k TV Solution  -  Socionext
Time Domain Neural Network  -  Toshiba
Movidius  -  Intel
Machine vision on a chip: non-mechanical laser radar enabled by liquid crystal waveguides  -  Analog Devices
Of categories and computers: a story unfolding  -  Tim Carstens
Scale out object storage  -  Keeper Technology
Practical Quantum Computing and the Rigetti Quantum Computer  -  Rigetti Quantum Computing
Reading Tea Leaves: Extrapolating meaning from plaintext size of encrypted blobs  -  Josh Pitts
Cassandra, Scale out database  -  Apple
Artificial Intelligence & Machine Learning: Entrepreurship & Technology Buildouts  -  CDL
Tensorflow  -  Google
Exa-scale IOT Network Designs for Machine Learning and Big Data  -  Kyndi, Inc

Program Committee

Chair: Bill Huffman Cadence (Tensilica)
Co-Chair: David Flynn, ARM

Yahya Sotoudeh, Intel
Jay Fleischman, AMD
Steve Miller, Intel
Pete Wilson, Kiva Design Groupe
Atsushi Hasegawa, Renesas
Yoshio Masubuchi, Toshiba
Jem Davies, ARM
Michael Allen, Analog Devices
Parker Thompson, Leviathan
Baron Von Oldenberg, Leviathan
Arun Majumdar, Kyndi, Inc
Richard Grisenthwaite, ARM


The workshop is "all inclusive". The workshop fee covers the event, housing and all food from dinner Sunday through lunch Wednesday.

Fees will be:

Early Late
after June 1
Usenix Members $995 $1095
Non-members $1095 $1195


Registration fees include the workshop, lodging and meals. The prices increase by $100 on June 5st.


The workshop has been held since 1974 and some of the past workshops are available online.

The executive committee can be found here.